10.6.10 Contention Between Br Write And Input Capture - Hitachi SH7032 Hardware Manual

10.6.10 Contention between BR Write and Input Capture

When a buffer register (BR) is being used as an input capture register and an input capture signal
is generated in the T3 state of the write cycle, the buffer operation takes priority over the BR write.
The timing is shown in figure 10.66.
write signal
Input capture
Figure 10.66 Contention between BR Write and Input Capture
298
T1
CK
Address
Internal
signal
GR
BR
BR write cycle
T2 T3
BR address
N
M
X
TCNT value
N