Notes And Precautions; Contention Between Tcnt Write And Clear - Hitachi SH7032 Hardware Manual

10.6

Notes and Precautions

This section describes contention and other matters requiring special attention during ITU
operation.
10.6.1

Contention between TCNT Write and Clear

If a counter clear signal occurs in the T3 state of a TCNT write cycle, clearing the counter takes
priority and the write is not performed. The timing is shown in figure 10.58.
Internal write signal
Counter clear signal
Figure 10.58 Contention between TCNT Write and Clear
290
TCNT write cycle by CPU
T1
CK
Address
TCNT
T2 T3
TCNT address
N H' 0000