Contention Between General Register Write And Input Capture; Note On Waveform Cycle Setting - Hitachi SH7032 Hardware Manual

10.6.8

Contention between General Register Write and Input Capture

If an input capture signal is generated during the T3 state of a general register write cycle, the
input capture transfer takes priority and the write to GR is not performed. The timing is shown in
figure 10.65.
write signal
Input capture
Figure 10.65 Contention between General Register Write and Input Capture
10.6.9

Note on Waveform Cycle Setting

When a counter is cleared by compare match, the counter is cleared in the last state in which the
TCNT value matches the GR value (when TCNT is updated from the matching count to the next
count). The actual counter frequency is therefore given by the following formula:
f = φ/(N + 1)
(f: counter frequency; φ: operating frequency; N: value set in GR)
T1
CK
Address
Internal
signal
TCNT
GR
GR write cycle
T2 T3
GR address
M
M
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