Standby Control Register (Sbycr) Power-Down State - Hitachi SH7032 Hardware Manual

Table A.53 RSTCSR Bit Functions
Bit Bit Name
7 Watchdog timer overflow flag
(WOVF)
6 Reset enable (RSTE)
5 Reset select (RSTS)
Note: * The microprocessor is not reset internally, but TCNT and TCSR within the WDT are reset.
A.2.53 Standby Control Register (SBYCR)
• Start Address: H'5FFFFBC
• Bus Width: 8/16/32
Register Overview:
Bit:
Bit name:
Initial value:
R/W:
Table A.54 SBYCR Bit Functions
Bit Bit Name
7 Standby (SBY)
6 Port high impedance (HIZ)
620
Value
0
1
0
1
0
1
7 6
SBY HIZ —
0 0
R/W R/W —
Value
0
1
0
1
Description
No TCNT overflow in watchdog timer mode
Clear Condition: WOVF read, then 0 written in
WOVF
TCNT overflow generated in watchdog timer
mode
No internal reset when TCNT overflows *
Internal reset when TCNT overflows
Power-on reset
Manual reset
5 4 3
— —
0 1 1
— —
Description
Shift to sleep mode on execution of SLEEP
instruction
Shift to standby mode on execution of SLEEP
instruction
Pin states held in standby mode
Pins change to high impedance in standby mode
(Initial value)
(Initial value)
(Initial value)
Power-Down State
2 1 0
— — —
1 1 1
— — —
(Initial value)
(Initial value)