Dma Channel Control Registers 0-3 (Chcr0-Chcr3) Dmac - Hitachi SH7032 Hardware Manual

A.2.27 DMA Channel Control Registers 0–3 (CHCR0–CHCR3)
• Start Address: H'5FFFF4E (channel 0), H'5FFFF5E (channel 1), H'5FFFF6E (channel 2),
H'5FFFF7E (channel 3)
• Bus Width: 8/16/32
Register Overview:
Bit:
Bit name:
Initial value:
R/W:
Bit:
Bit name:
Initial value:
R/W:
Notes: *1 Only 0 can be written, to clear the flag.
*2 Writing is valid only for CHCR0 and CHCR1.
15 14
DM1 DM0 SM1
0 0
R/W R/W R/W
7 6
AM AL
0 0
2 2
R/W * R/W * R/W *
13 12 11
SM0 RS3
0 0 0
R/W R/W
5 4 3
DS TM TS
0 0 0
2
R/W R/W
DMAC
10 9
RS2 RS1 RS0
0 0
R/W R/W R/W
2 1
IE TE DE
0 0
1
R/(W) *
R/W R/W
8
0
0
0
591