Cpu Interface; 16-Bit Accessible Registers - Hitachi SH7032 Hardware Manual

10.3

CPU Interface

10.3.1

16-Bit Accessible Registers

The timer counters (TCNT), general registers A and B (GRA, GRB), and buffer registers A and B
(BRA, BRB) are 16-bit registers. The SH CPU can access these registers a word at a time using a
16-bit data bus. Byte access is also possible. Read and write operations performed on TCNT in
word units are shown in figures 10.6 and 10.7. Byte-unit read and write operations on TCNTH and
TCNTL are shown in figures 10.8 to 10.11.
Internal data bus
H
CPU
L
Internal data bus
H
CPU
L
Internal data bus
H
CPU
L
Figure 10.8 TCNT Access (CPU to TCNT (Upper Byte))
Bus
interface
Figure 10.6 TCNT Access (CPU to TCNT (Word))
Bus
interface
Figure 10.7 TCNT Access (TCNT to CPU (Word))
Bus
interface
TCNTH TCNTL
TCNTH TCNTL
TCNTH TCNTL
H
Module
L
data bus
H
Module
L
data bus
H
Module
L
data bus
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