Break Bus Cycle Register (Bbr) - Hitachi SH7032 Hardware Manual

6.2.3

Break Bus Cycle Register (BBR)

The break bus cycle register (BBR) is a 16-bit read/write register that selects the following four
break conditions:
• CPU cycle or DMA cycle
• Instruction fetch or data access
• Read or write
• Operand size (byte, word, longword).
A reset initializes BBR to H'0000. It is not initialized in standby mode.
Bit:
Bit name:
Initial value:
R/W:
Bit:
Bit name:
Initial value:
R/W:
• Bits 15–8 (Reserved): These bits are always read as 0. The write value should always be 0.
• Bits 7 and 6 (CPU Cycle/DMA Cycle Select (CD1 and CD0)): CD1 and CD0 select whether to
break on CPU and/or DMA bus cycles.
Bit 7: CD1
0
1
86
15 14
— —
0 0
— —
7 6
CD1 CD0
0 0
R/W R/W
Bit 6: CD0
0
1
0
1
13 12 11
— — —
0 0
— — —
5 4
ID1 ID0 RW1
0 0
R/W R/W R/W
Description
No break interrupt occurs
Break only on CPU cycles
Break only on DMA cycles
Break on both CPU and DMA cycles
10 9
— —
0 0 0
— —
3 2 1
RW0 SZ1
0 0 0
R/W R/W
8
—
0
—
0
SZ0
0
R/W
(Initial value)