Register Tables; Serial Mode Register (Smr) Sci; A.2 Register Tables - Hitachi SH7032 Hardware Manual

A.2

Register Tables

A.2.1 Serial Mode Register (SMR)
• Start Address: H'5FFFEC0 (channel 0), H'5FFFEC8 (channel 1)
• Bus Width: 8/16
Register Overview:
Bit:
Bit name:
Initial value:
R/W:
Table A.3 SMR Bit Functions
Bit Bit name
7 Communication mode (C/A)
6 Character length (CHR)
5 Parity enable (PE)
4 Parity mode (O/E)
3 Stop bit length (STOP)
2 Multiprocessor mode (MP)
1,0 Clock select 1, 0 (CKS1, CKS0)
Note: * When 2 or more bits are treated as a group, the left side is the upper bit and the right the
lower bit.
7 6
C/A CHR PE
0 0
R/W R/W R/W
Value*
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
5 4 3
O/E STOP
0 0 0
R/W R/W
Description
Asynchronous mode
Synchronous mode
8-bit data
7-bit data
Parity bit addition and check disable
Parity bit addition and check enable
Even parity
Odd parity
1 stop bit
2 stop bits
Multiprocessor function disabled (Initial value)
Multiprocessor function selected
φ clock
0
φ/4 clock
1
φ/16 clock
0
φ/64 clock
1
2 1
MP CKS1 CKS0
0 0
R/W R/W R/W
(Initial value)
(Initial value)
(Initial value)
(Initial value)
(Initial value)
(Initial value)
SCI
0
0
565