Block Diagram - Hitachi SH7032 Hardware Manual

• Transfer requests
 External request (From DREQ pins (channels 0 and 1 only). DREQ can be detected either
by edge or by level)
 Requests from on-chip supporting modules (serial communication interface (SCI), A/D
converter (A/D), and 16-bit integrated timer pulse unit (ITU))
 Auto-request (the transfer request is generated automatically within the DMAC)
• Selectable bus modes: Cycle-steal mode or burst mode
• Selectable channel priority levels: Fixed, round-robin, or external-pin round-robin modes
• CPU can be asked for interrupt when data transfer ends
• Maximum transfer rate
 20 M words/s (320 MB/s)
For 5 V and 20 MHz
Bus mode: Burst mode
Transmission size: Word
9.1.2

Block Diagram

Figure 9.1 shows a block diagram of the DMAC.
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