Timer Interrupt Enable Register (Tier) - Hitachi SH7032 Hardware Manual

• Bit 1 (Input Capture/Compare Match B (IMFB)): IMFB indicates a GRB compare match or
input capture.
Bit 1: IMFB
0
1
• Bit 0 (Input Capture/Compare Match A (IMFA)): IMFA indicates a GRA compare match or
input capture.
Bit 0: IMFA
0
1

10.2.12 Timer Interrupt Enable Register (TIER)

The timer status interrupt enable register (TIER) is an eight-bit read/write register that controls
enabling/disabling of overflow interrupt requests and general register compare match/input capture
interrupt requests. TIER is initialized to H'F8 or H'78 by a reset and in standby mode. Each ITU
channel has one TIER.
Description
Clearing condition: Read IMFB when IMFB = 1, then write 0 in IMFB
Setting conditions:
•
GRB is functioning as an output compare register and TCNT =
GRB
•
GRB is functioning as an input capture register and the value of
TCNT is transferred to GRB by an input capture signal
Description
Clearing condition:
Read IMFA when IMFA = 1, then write 0 in IMFA
DMAC is activated by an IMIA interrupt (only channels 0–3)
Setting conditions:
•
GRA is functioning as an output compare register and TCNT =
GRA
•
GRA is functioning as an input capture register and the value of
TCNT is transferred to GRA by an input capture signal
(Initial value)
(Initial value)
247