Register Configuration; Register Descriptions; Timer Counter (Tcnt) - Hitachi SH7032 Hardware Manual

12.1.4

Register Configuration

Table 12.2 summarizes the three WDT registers. They are used to select the clock, switch the
WDT mode, and control the reset signal.
Table 12.2 WDT Registers
Name
Timer control/status register
Timer counter
Reset control/status register
Notes: *1 Write by word transfer. A byte or longword write cannot be used.
*2 Read by byte transfer. The correct value cannot be obtained by a word or longword
read.
*3 Only 0 can be written in bit 7, to clear the flag.
*4 Only the values of bits A27–A24 and A8–A0 are valid; bits A23–A9 are ignored. For
details on the register addresses, see section 8.3.5, Area Descriptions
12.2

Register Descriptions

12.2.1

Timer Counter (TCNT)

TCNT is an eight-bit readable and writable up-counter. TCNT differs from other registers in that it
is more difficult to write. See section 12.2.4, Notes on Register Access, for details. When the timer
enable bit (TME) in the timer control/status register (TCSR) is set to 1, the timer counter starts
counting pulses of an internal clock source selected by clock select bits 2–0 (CKS2–CKS0) in
TCSR. When the value of TCNT overflows (changes from H'FF to H'00), a watchdog timer
overflow signal (WDTOVF) or interval timer interrupt (ITI) is generated, depending on the mode
selected with the WT/IT bit in TCSR. TCNT is initialized to H'00 by a reset and when the TME
bit is cleared to 0. It is not initialized in standby mode.
Bit:
Bit name:
Initial value:
R/W:
Abbreviation R/W
TCSR
TCNT
RSTCSR
7 6
0 0
R/W R/W R/W
Initial
Value
3
R/(W) *
H'18
R/W H'00
3
R/(W) *
H'1F
5 4 3
0 0 0
R/W R/W
4
Address *
1
Write * Read *
H'5FFFFB8 H'5FFFFB8
H'5FFFFB9
H'5FFFFBA H'5FFFFBB
2 1
0 0
R/W R/W
2
0
0
R/W
337