Break Bus Cycle Register (Bbr) Ubc - Hitachi SH7032 Hardware Manual

A.2.39 Break Bus Cycle Register (BBR)
• Start Address: H'5FFFF98
• Bus Width: 8/16/32
Register Overview:
Bit:
Bit name:
Initial value:
R/W:
Bit:
Bit name:
Initial value:
R/W:
Table A.40 BBR Bit Functions
Bit Bit name
7,6 CPU cycle/DMA cycle 0
select (CD1, CD0)
5,4 Instruction fetch/data
access select
(ID1, ID0)
3,2 Read/write select
(RW1, RW0)
1,0 Operand size select
(SZ1, SZ0)
15 14 13
— — —
0 0
— — —
7 6
CD1 CD0 ID1
0 0
R/W R/W R/W
Value Description
0 User break interrupt not generated
0 1 CPU cycle is break condition
1 0 DMA cycle is break condition
1 1 CPU cycle and DMA cycle are both break conditions
0 0 User break interrupt not generated
0 1 Instruction fetch cycle is break condition
1 0 Data access cycle is break condition
1 1 Instruction fetch cycle and data access cycle are both
break conditions
0 0 User break interrupt not generated
0 1 Read cycle is break condition
1 0 Write cycle is break condition
1 1 Read cycle and write cycle are both break conditions
0 0 Operand size not included in the break conditions
0 1 Byte access is break condition
1 0 Word access is break condition
1 1 Longword access is break condition
12 11
— —
0 0 0
— —
5 4 3
ID0 RW1
0 0 0
R/W R/W
10 9
— — —
0 0
— — —
2 1
RW0 SZ1 SZ0
0 0
R/W R/W R/W
(Initial value)
(Initial value)
(Initial value)
(Initial value)
UBC
8
0
0
0
605