Register Configuration - Hitachi SH7032 Hardware Manual

9.1.4

Register Configuration

Table 9.2 summarizes the DMAC registers. The DMAC has a total of 17 registers. Each channel
has four control registers. One other control register is shared by all channels.
Table 9.2 DMAC Registers
Chan-
nel Name
DMA source address register 0 SAR0 *
0
DMA destination address
register 0
DMA transfer count register 0
DMA channel control register 0 CHCR0
DMA source address register 1 SAR1 *
1
DMA destination address
register 1
DMA transfer count register 1
DMA channel control register 1 CHCR1
DMA source address register 2 SAR2 *
2
DMA destination address
register 2
DMA transfer count register 2
DMA channel control register 2 CHCR2
DMA source address register 3 SAR3 *
3
DMA destination address
register 3
DMA transfer count register 3
DMA channel control register 3 CHCR3
Shar- DMA operation register
ed
Notes: *1 Only 0 can be written in bit 1 of CHCR0–CHCR3, to clear flags.
*2 Only 0 can be written in bits 1 and 2 of DMAOR, to clear flags.
*3 Access SAR0–SAR3, DAR0–DAR3, and TCR0–TCR3 by longword or word. If byte
access is used when writing, the value of the register contents will be undefined; if used
when reading, the value read will be undefined.
*4 Only the values of bits A27–A24 and A8–A0 are valid; bits A23–A9 are ignored. For
details on the register addresses, see section 8.3.5, Area Descriptions.
Abbrevi- Initial
ation R/W Value
3
R/W Undefined
3
DAR0 *
R/W Undefined
3
TCR0 *
R/W Undefined
1
R/(W) *
H'0000
3
R/W Undefined
3
DAR1 *
R/W Undefined
3
TCR1 *
R/W Undefined
1
R/(W) *
H'0000
3
R/W Undefined
3
DAR2 *
R/W Undefined
3
TCR2 *
R/W Undefined
1
R/(W) *
H'0000
3
R/W Undefined
3
DAR3 *
R/W Undefined
3
TCR3 *
R/W Undefined
1
R/(W) *
H'0000
2
R/(W) *
DMAOR H'0000
Access
4
Address* Size
H'5FFFF40 16, 32
H'5FFFF44 16, 32
H'5FFFF4A 16, 32
H'5FFFF4E 8, 16, 32
H'5FFFF50 16, 32
H'5FFFF54 16, 32
H'5FFFF5A 16, 32
H'5FFFF5E 8, 16, 32
H'5FFFF60 16, 32
H'5FFFF64 16, 32
H'5FFFF6A 16, 32
H'5FFFF6E 8, 16, 32
H'5FFFF70 16, 32
H'5FFFF74 16, 32
H'5FFFF7A 16, 32
H'5FFFF7E 8, 16, 32
H'5FFFF48 8, 16, 32
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