Timer Mode Register (Tmdr) Itu - Hitachi SH7032 Hardware Manual

A.2.12 Timer Mode Register (TMDR)
• Start Address: H'5FFFF02
• Bus Width: 8
Register Overview:
Bit:
Bit name:
Initial value:
R/W:
Note: * Undetermined
Table A.13 TMDR Bit Functions
Bit Bit name
6 Phase counting mode (MDF)
5 Flag direction (FDIR)
4 PWM mode 4 (PWM4)
3 PWM mode 3 (PWM3)
2 PWM mode 2 (PWM2)
1 PWM mode 1 (PWM1)
0 PWM mode 0 (PWM0)
576
7 6 5
— MDF FDIR
* 0 0
— R/W R/W
Value
0
1
0
1
0
1
0
1
0
1
0
1
0
1
4 3
PWM4 PWM3
0 0
R/W R/W
Description
Channel 2 operates normally
Channel 2 in phase count mode
OVF of TSR2 set to 1 when TCNT2 overflows or
underflows
OVF in TSR2 set to 1 when TCNT2 overflows
Channel 4 operates normally
Channel 4 in PWM mode
Channel 3 operates normally
Channel 3 in PWM mode
Channel 2 operates normally
Channel 2 in PWM mode
Channel 1 operates normally
Channel 1 in PWM mode
Channel 0 operates normally
Channel 0 in PWM mode
2 1
PWM2 PWM1 PWM0
0 0
R/W R/W
(Initial value)
(Initial value)
(Initial value)
(Initial value)
(Initial value)
(Initial value)
(Initial value)
ITU
0
0
R/W