Refresh Control Register (Rcr) Bsc - Hitachi SH7032 Hardware Manual

Superh risc engine
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A.2.46
Refresh Control Register (RCR)
• Start Address: H'5FFFFAC
• Bus Width: 8/16/32 (read), 16 (write)
Register Overview:
Bit:
Bit name:
Initial value:
R/W:
Bit:
Bit name:
Initial value:
R/W:
Table A.47 RCR Bit Functions
Bit
Bit Name
7
Refresh control (RFSHE)
6
Refresh mode (RMODE)
5,4
Wait state insertion CBR
refresh 1,0 (RLW1, RLW0)
614
15
14
0
0
7
6
RFSHE RMODE
RLW1
0
0
R/W
R/W
Value
0
1
0
1
0
0
1
1
13
12
11
0
0
5
4
RLW0
0
0
R/W
R/W
Description
No refresh control
(RTCNT can be used as an interval timer)
Refresh control
CAS-before-RAS refresh performed
Self-refresh performed
0
1-cycle wait state inserted
1
2-cycle wait state inserted
0
3-cycle wait state inserted
1
4-cycle wait state inserted
10
9
0
0
0
3
2
1
0
0
0
BSC
8
0
0
0
(Initial value)
(Initial value)
(Initial value)

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