Configuration Resistors Register - GE SBC330 3U VPX Hardware Reference Manual

Table of Contents

Advertisement

6.19 Configuration Resistors Register

Table 6-5 Register to Speed Mapping
SYSCLK
SYSCLK to
Frequency
Platform Clock
(MHz)
Multiplier
66.66
2
66.66
3
66.66
4
66.66
5
66.66
6
66.66
8
66.66
9
66.66
6
66.66
6
66.66
9
70 SBC330 3U VPX Single Board Computer
SBC330 has a resistor‐defined configuration for initial Platform and Processor 
Core speed. The Platform and Processor Core speed can be changed via the Sticky 
registers for the Platform and Core Multipliers, which take effect after a reboot so 
long as power is maintained.
Three signal lines to the FPGA are pulled high or low by resistors giving eight 
hardware defined speed configuration options from power up.
Chip Select
CS2
Offset
0x00AC
LAD Bit
Reg Bit
R/W
15 to 13
0 to 2
R
Table 6‐5 shows the value read in the register versus the SBC330 speed 
configuration set up.
Platform
Platform
Frequency
to Core
(MHz)
Multiplier
133.3
2.0
200
2.5
266.6
2.5
333
2.5
400
2.5
533.3
2.5
600
2.0
400
3.0
400
3.5
600
2.5
NOTE
The highlighted rows in the table indicate the default speeds that align to SBC330 Product Codes.
The code '000' in the FPGA interprets as PLATFORM_MULTIPLIER = 6x and 
CORE_MULTIPLIER = 2.5x. 
The SBC330 system clock is 66.66 MHz, which means the Platform speed is 
(66.66 x 6 = 400 MHz) and the Core Speed is (2.5x 400 = 1000 MHz).
A total of six configuration resistors control the default platform and core speed 
of the processor. These are R570, R569, R571 (10K pull‐ups to P3V3) and R215, 
R244, R245 (1K pull‐downs to ground). R570 & R215 control CFG(0), R569 & R244 
control CFG(1), and R571 & R245 control CFG(2).
Description
Straight binary of resistor pull-downs and
pull-ups on signals CPLD_DEBUG(0:2)
Core
CFG_SYS
Frequency
_PLL[0:3]
(MHz)
266
500
665
833
1000
0110
b
1333
1000
b
1200
1001
b
1200
0110
b
1400
0110
b
1500
1001
b
Reset Value
Depends on
jumper
settings
CFG_
CFG_CORE
PLATFORM
_PLL[0:4]
_FREQ
0
0
0
0
01100
0
b
01100
1
b
01000
1
b
10000
1
b
11100
1
b
01100
1
b
Publication No. SBC330-0HH/3
Resistor
CFG binary
value
CPLD_CFG
[0..2]
None
Implement
0 001
b
1 010
b
2 000
b
3 011
b
4 100
b
5 101
b
6 110
b
7 111
b

Hide quick links:

Advertisement

Table of Contents
loading

Table of Contents