Pci Express To Pci Bridge; Pci Bus; Local Bus - GE SBC330 3U VPX Hardware Reference Manual

5.5 Local Bus

34 SBC330 3U VPX Single Board Computer

5.4.3 PCI Express to PCI bridge

The SBC330 uses a PLX PEX8114 to bridge between PCIe and PCI, which is
required only because the NEC UPD720101 USB controller only has a PCI
connection. The bridge operates in its forward mode (PCIe‐to‐PCI) on‐board the
SBC330. The bridge is connected to the switch via a x2 PCI Express link, allowing
a maximum bandwidth of 500 MBytes in each direction.
The bridge also contains the arbiter for the PCI bus. Arbitration is minimal, as the
NEC UPD720101 is the only device on the bus, and so the USB interface benefits
from the full bandwidth of the PCI bus. The Bridge runs its PCI side at 32‐bit,
33 MHz to match the maximum clock frequency of the NEC UPD720101 PCI to
USB device.
The bridge is configured by hardware strapping, but has an associated serial
EEPROM (ATMEL 25256) that can also be used to configure registers in the device
if required. The EEPROM is write‐protected by the NVMRO signal from the VPX
backplane.
The PEX8114 can report any errors detected to the processor via in‐band PCIe
Message Signaled Interrupts (MSI) or as legacy PCI INTx interrupt delivery.

5.4.4 PCI Bus

The 32‐bit PCI bus on the SBC330 runs at 33 MHz and is connected between the
PEX8114 Bridge and the NEC UPD720101 USB2.0 controller only. The NEC device
is on IDSEL line #19; the Bridge does not need an IDSEL in its forward mode.
The MPC8461D local bus is a 32‐bit multiplexed address/data bus that is used to
access the Local Bus Control FPGA and the Flash.
The Flash address lines are connected to a de‐multiplexed address bus created by
the Local Bus Control FPGA. The MPC8641D local bus controller provides up to
eight chip selects, which are allocated to devices as defined in the table below. The
minimum possible window size is 32 KBytes.
In the current release of FPGA firmware (TB0785‐003 – August 2008) the
implementation of the Chip Selects is as shown in the table below.
CAUTION
This is subject to change in future firmware or PCB artwork where User Flash may be partitioned
for core 0 and core 1 accesses.
Table 5-8 Flash Memory Allocation
Local Bus
Target
Chip Select
0 Boot Flash
1 User Flash
2 FPGA functions
3 to 7 Not used
Device Width
32-bit
32-bit
32-bit (many registers 16-bit)
-
Window Size
8/16 MBytes
Up to 512 MBytes
32 KBytes
-
Publication No. SBC330-0HH/3