Interrupt Mask Register - GE SBC330 3U VPX Hardware Reference Manual

Publication No. SBC330-0HH/3

6.2.2 Interrupt Mask register

Chip Select CS2
Offset 0x0004
LAD Bit Reg Bit R/W
23 0 R/W
22 1 R/W
21 2 R/W
20 3 R/W
19 4 R/W
18 5 R/W
17 6 R/W
16 7 R/W
15 8/0 orig R/W
14 9 R/W
13 10 R/W
12 11 R/W
11 12 R/W
10 13 R/W
9 14 R/W
8 15 R/W
7 16 R/W
6 17 R/W
5 18 R/W
4 19 R/W
3 20 R/W
2 21 R/W
1 22 R/W
0 23 R/W
This register defaults to 0x0000 (all interrupts masked) at power up. Writing a '1'
in this register unmasks the interrupt in the Interrupt register, and to the CPU.
Software should unmask the CPU_HOT_ALERT and the
THERMAL_SHUTDOWN signals, which indicate the CPU temperature. Unless
software unmasks these bits, the processor will not know if it is in danger of
overheating and to store any useful information. The THERMAL_SHUTDOWN
signal actually cuts the power to the board's main ICs by signaling to the Lattice
Power Manager to turn off most of the supplies. The 5V input voltage and the
P3V3_LIN rail remain powered to maintain RTC and BMM functions.
Interrupt Source
GPIO bit (0)
GPIO bit (1)
GPIO bit (2)
GPIO bit (3)
GPIO bit (4)
GPIO bit (5)
GPIO bit (6)
GPIO bit (7)
Ethernet PHY on ETSEC 1
Ethernet PHY on ETSEC 3
USB INT A
USB INT B
USB INT C
CPU_HOT_ALERT
THERMAL SHUTDOWN
PEX8114_INT_A
EXTERNAL_INT (if enabled)
REAL TIME CLOCK INT
WATCHDOG 0 INTERRUPT
WATCHDOG 1 INTERRUPT
(reserved for expansion)
(reserved for expansion)
(reserved for expansion)
(reserved for expansion)
Reset Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
FPGA Registers 49