Id Register; Flash Control Register - GE SBC330 3U VPX Hardware Reference Manual

6.12 ID Register

6.13 Flash Control Register

Publication No. SBC330-0HH/3
All boards are assigned an ID. The ID for the SBC330 is 0x30. This fixed value is
held in this register.
Chip Select CS2
Offset 0x0064 and 0x0068
Reset value 0x30 ‐ Defines the SBC330 Product
LAD Bit Reg Bit R/W
15 0 R
14 1 R
13 2 R
12 3 R
11 4 R
10 5 R
9 6 R
8 7 R
The Flash Control Register allows the SBC330 to read the state of the Flash
Control jumpers. See Section 4.3
Flash jumpers. The names of the jumper signals in this document relate to the net
name that they connect to (user manuals may describe these differently.)
• CPLD_JMP1 selects AMP or SMP mode
• CPLD_JMP2 overrides any software setting of unlocking the password.
Fitting this jumper locks the password registers and the boot area
• FLASH_BOOT_SEC1 and FLASH_BOOT_SEC2 form binary combinations
that determine the address of the boot Flash areas as described in
Section 4.3
The initial value depends on jumper settings. Fitted jumpers are indicated by a '1',
(which is opposite to the signal level).
The Password Control bit is low ('0'), so that the password is not visible at power
up.
Page mode is disabled (low ‐ '0'). Page mode is not implemented for the initial
release. Page mode bits are initialized to 0000
large Flash memory sizes) are unlikely to be implemented on the SBC330. If they
are, the page mode control will be added into this register.
Chip Select CS2
Offset 0x0044
Reset value Depends on jumper settings
Description
ID reg bit 0
ID reg bit 1
ID reg bit 2
ID reg bit 3
ID reg bit 4
ID reg bit 5
ID reg bit 6
ID reg bit 7
for more information on the operation of the
. Page Mode functions (for very
b
Reset Value
0
0
0
0
1
1
0
0
FPGA Registers 63