P10 Header; Flash Software Protection Password Visibility; Flash Password/Boot Sector Protection; Boot Flash Image Selection - GE SBC330 3U VPX Hardware Reference Manual

4.3 P10 Header

Errata
May 2011
20 SBC330 3U VPX Single Board Computer
The P10 header is dedicated to Flash memory options which affect booting.
Table 4-1
Jumper Description
Pin 1 & pin 2

Flash Software Protection Password visibility

Pin 3 & pin 4 Flash Password and boot sector protection
Pin 5 & pin 6 Binary combination with pins 7 & 8
Pin 7 & pin 8 Binary combination with pins 5 & 6
4.3.1 Flash software protection password visibility
Pins 1 and 2 must be linked to allow software to alter the Spansion‐termed
"persistent sector protection", which remains unchanged following a reset or a
power‐cycle. See Section 5.3.7
software is prevented from altering any previously configured sector protection,
because the password stored in the FPGA is made invisible to the Software.
Examination of the Flash Password register reveals ASCII code 'DataSafe' if the
link is fitted or 'locklock' if the link is not fitted. The state of this link is reflected in
the Flash Control register.

4.3.2 Flash password/Boot Sector protection

Without pins 3 and 4 being linked, no write access is allowed to the boot sector,
which prevents any erroneous user software remapping of User Flash areas,
overwriting boot sector Flash information. The address region protected is the top
8 MByte region of the local bus (0xFF80 0000 to 0xFFFF FFFF), which comprises all
four of the separate 2 MByte core 0 boot sites.

4.3.3 Boot Flash image selection

The Boot Flash for processing core 0 is divided into four 2 MByte sections named
Main, Alternate, Extended, and BANC (Boot Area Non Corruptible). These allow
for three different boot images to be loaded from the Flash, plus (when available)
a factory‐programmed boot image that allows the user to recover if a non‐
bootable image is erroneously put into Flash. The different boot images allow the
board to boot different code from power up. For instance, it enables GEIP to
program both Functional Test Code (FTS) and VxWorks Operating Systems
concurrently into the same board to aid diagnostics. Another example may be to
allow booting as a PCIe root complex or a PCIe end‐point on either of the two
PCIE‐Express ports, which may be useful in multi‐board applications.
Pins 5‐6 and 7‐8 form a binary combination that alters the order of the 2 MByte
(0x2000) boot regions in the Flash memory and selects which image is used at
boot time. The state of these jumper links is reflected in the Flash Control Register.
for further details. If the link is not fitted, the
Sense when fitted
Password visible
Boot sector writable
Further explained
Further explained
Publication No. SBC330-0HH/3