Core Multiplier Register - GE SBC330 3U VPX Hardware Reference Manual

6.8 Core Multiplier Register

Publication No. SBC330-0HH/3
The Core Multiplier in the 8641D takes the platform frequency as its source and
multiplies it by a selectable ratio to produce the core frequency. This ratio ranges
from 2:1 to 4.5:1 in steps of 0.5.
This register is loaded at power‐up from a configuration resistor setting. The
register is connected to the pins LDP[0:3] and LA[27], and drives during power‐
on/reset.
The register is 'Sticky' through a front‐panel hard reset, i.e. the core speed can be
adjusted by writing to this register and asserting the Reset signal. The register
returns to its default following a power cycle.
Chip Select CS2
Offset 0x0024
LAD Bit Reg Bit R/W
15 0 R/W
14 1 R/W
13 2 R/W
12 3 R/W
11 4 R/W
The meaning of the bits is reproduced here from the 8641D specification:
Table 6-4
Signal Binary
LDP[0:3], LA27 0_1000
0_1100
1_0000
1_1100
1_0100
0_1110
Description Reset Value
DP(0) Variant dependent
DP(1) Variant dependent
DP(2) Variant dependent
DP(3) Variant dependent
ADD_27 Variant dependent
Platform Clock (MPX
Comments
Bus) Multiplier
2:1
2.5:1 Default for 400 MHz/1 GHz boards
3:1 Default for 500 MHz/1.5 GHz boards
3.5:1
4:1
4.5:1
FPGA Registers 57