User Flash; Paged Flash Mode - GE SBC330 3U VPX Hardware Reference Manual

Publication No. SBC330-0HH/3
By default, shipped boards have the top 8 MBytes reserved as boot Flash, and the
Core 1 Boot bit in the Flash Control Register (offset 0x0044, see the Registers
section) is set to 0. If core 1 is required to boot from a different image, then the
core 0 boot loader must include code to set the Core 1 Boot bit to ʹ1ʹ before
releasing core 1. See the SBC330 software manual for further description of
BootROM loaders.
The BANC (Boot Area Non Corruptible) recovery boot image area contains a
256 KByte factory‐programmed boot image, shared by both processing cores,
allowing the Flash to be reprogrammed if other boot images become corrupted.
This area is protected by hardware and is not writeable by the user. The
remainder of this 2 MByte boot image can be used to store BIT results.
The boot Flash is accessed using Chip Select 0 on the Local Bus Controller of the
MPC8641D, and is configured as the default boot location for the PowerPC reset
vector (0xFFF0 0100). The boot areas are mapped into a 16 MByte window.
The active boot image for Core 0 is set using P10 pins 5 to 8 as described in
Chapter 4 • . The Core 1 boot region is either the same as the Core 0 boot region
or is the same offset by 8 MBytes if the Core 1 Alternative Boot bit is set in the
Flash register. The Core 0 and Core 1 boot regions are linked because there are
insufficient jumpers on SBC330 to make them completely independent.

5.3.5 User Flash

Any Flash that is not used as Boot Flash is designated as User Flash and is
intended to hold user application code or data.
User Flash is accessed using Chip Select CS1 on the Local Bus Controller of the
MPC8641D. Chip Select 1 is intended for use by Processing Core 0 and may be
used to access all areas of Flash, as required when using a single‐core or SMP
system.
The 8 MBytes of Boot Flash appears at the top of the User Flash area, with the four
boot images appearing in their physical locations (i.e. 0xEF80 0000 to
0xEFFF FFFF mirrors 0xFF80 0000 to 0xFFFF FFFF). Chip Select 1 accesses are
unaffected by the boot‐swap jumper links. Programming at a given offset
therefore always stores at that given offset.
For example, using CS0, programming at 0xFFF0 0000 may actually program into
Flash at 0xFFFD 0000 if P10 pins 5 and 6 are linked. Using CS1, programming
0xEFF0 0000, programs into Flash at 0xEFF0 0000 (which is also equivalent to
0xFFF0 0000), regardless of the Flash boot link settings.

5.3.6 Paged Flash Mode

CAUTION
This mode is only available with SBC330 boards that have 512 MByte of Flash fitted.
When an SBC330 is fitted with 512 MBytes of Flash, due to limitations on the size
of the processor memory map, a paged mode is provided where the User Flash
area is divided into a number of 128 MByte pages, with separate pages selectable
for Chip Select 1 (CS1). This mode is controlled by two Flash page bits in the Flash
Control Register. Paged mode is disabled by default, with the effect that CS1
points to the top page.
Functional Description 29