Board Id Register (0X600); Board Revision Register (0X601); Board Configuration Register 1 (0X602); Board Configuration Register 2 (0X603) - GE OpenVPX VPXcel6 SBC622 Hardware Reference Manual

The control and status registers exist for controlling or reading the status of the
hardware. The addresses are as seen by the processor. In the following register
descriptions, the bit significance is shown in little‐endian mode (i.e. from the
viewpoint of the processor). MSB = D7, LSB = D0

3.2.1 Board ID Register (0x600)

This reads back 0x56, the number assigned to the SBC622.

3.2.2 Board Revision Register (0x601)

This provides information on the build state of the SBC622.

Table 3-2 Board Revision Register (0x601)

Bits
D7 to D5
D4 to D0

3.2.3 Board Configuration Register 1 (0x602)

This register is not implemented on the SBC622.

3.2.4 Board Configuration Register 2 (0x603)

The SBC622 only implements bit 0 of this register.

Table 3-3 Board Configuration Register 2 (0x603)

Bit
D7
D6
D5
D4
D3
D2
D1
D0
Meaning
Number revision (artwork level) of the hardware build state:
1 = Revision 1
2 = Revision 2
3 = Revision 3
4 = Revision 4
Letter revision of the hardware build state:
0x0 = Revision A
0x1 = Revision B
0x18 = Revision Y
0x19 = Revision YA
0x1F = Revision YG
Meaning
PMC READY
1 = Not ready
0 = Ready
RESERVED. Reads '0'
RESERVED. Reads '0'
Reserved. Reads '0'
RESERVED. Reads '0'
DBA~ (unused signal that comes from the Test connector)
1 = Not active
0 = Active
RESERVED. Reads '0'
VPX System Controller
1 = SBC622 is System Controller
0 = SBC622 is not System Controller
CPLD Control and Status Registers 51