Interrupt Edge/Level Register - GE SBC330 3U VPX Hardware Reference Manual

50 SBC330 3U VPX Single Board Computer

6.2.3 Interrupt Edge/Level register

Chip Select CS2
Offset 0x0008
Reset value 0x0000
LAD Bit Reg Bit R/W
23 0 R/W
22 1 R/W
21 2 R/W
20 3 R/W
19 4 R/W
18 5 R/W
17 6 R/W
16 7 R/W
15 8/0 (orig) R/W
14 9 R/W
13 10 R/W
12 11 R/W
11 12 R/W
10 13 R/W
9 14 R/W
8 15 R/W
7 16 R/W
6 17 R/W
5 18 R/W
4 19 R/W
3 20 R/W
2 21 R/W
1 22 R/W
0 23 R/W
This register defines whether the incoming interrupt is dealt with as a 'Level' or
an 'Edge' signal. The default at power‐up and reset is 0x0000, which dictates all
'Level' interrupts.
Setting a bit to 1 changes an interrupt to 'Edge'. Edge interrupts are latched in the
Interrupt register which then needs to have the same bit written‐to as a '0' for the
interrupt to be cleared.
Interrupt Source
GPIO bit (0)
GPIO bit (1)
GPIO bit (2)
GPIO bit (3)
GPIO bit (4)
GPIO bit (5)
GPIO bit (6)
GPIO bit (7)
Ethernet PHY on ETSEC 1
Ethernet PHY on ETSEC 3
USB INT A
USB INT B
USB INT C
CPU_HOT_ALERT
THERMAL SHUTDOWN
PEX8114_INT_A
EXTERNAL_INT (if enabled)
REAL TIME CLOCK INT
WATCHDOG 0 INTERRUPT
WATCHDOG 1 INTERRUPT
(Reserved for expansion)
(Reserved for expansion)
(Reserved for expansion)
(Reserved for expansion)
Publication No. SBC330-0HH/3