Jtag Boundary Scan Circuitry; Configuration Headers - GE C2K Hardware Reference Manual

4.21 JTAG Boundary Scan Circuitry

The JTAG circuitry provides a boundary scan chain for checking major components on C2K for
open and short circuits, and grounds. It can also be configured for special functions such as COP
software debugging through the COP header (J6) and C8051 Microcontroller software debugging.
The JTAG Scan chain can use the cPCI backplane through cPCI_J1 (default) or the on-board
JTAG header (J7) as its interface.
The components included in the JTAG Boundary Scan Chain include:
• IPMI C8051 Microcontroller
• IPMI CPLD
• FPGA EEPROM
• FPGA
• G31244 Serial ATA Controller
• PCI 6254 cPCI Bridge
• PCI2050B PCI/PCI Bridge
• PMC0 site
• PMC1 site
• MPC7448 processor
• MV64460 System Controller

4.21.1 Configuration Headers

C8051 Microcontroller Isolation (P11)
The C8051 Isolation header/jumper (P11) isolates the C8051 Microcontroller from the JTAG
Boundary Scan Chain for software debugging as shown in Figure 4-4 on page 4-18. When a
jumper is installed on header P11, the C8051 Controller is isolated from the JTAG Scan chain (see
"C8051 Debug (P11)" on page 2-3). When a jumper is not installed, all JTAG-equipped devices
on the board are included in the JTAG chain.
COP Port Enable (J6)
The COP Port Enable header/jumper (P10) enables a bus switch to isolate the MPC7448
processor from the JTAG Scan chain, and connects the COP header to the processor for
debugging application code as shown in Figure 4-4 on page 4-18 (see "COP_EN (P10)" on
page 2-3). When a jumper is installed on header P10, the COP header J6 provides the interface to
the processor's COP interface. When a jumper is not installed, all JTAG-equipped devices on the
board are included in the JTAG chain.
4-17
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