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5.7.2 Real Time Clock
The SBC330 provides an Epson RX8581_NB Real Time Clock (RTC) device with a
minimum of 1 second resolution. The RTC can be powered from the VPX
backplane P3V3_AUX or the VBAT signal when the main power supply is
removed. The interrupt output of the RTC can generate an interrupt to either
processor core, via the Local Bus FPGA. The 'programmable square wave' output
from this device is also connected to the FPGA. However, current firmware does
not make any use of the signal.
5.7.3 Elapsed Time Indicator
A Dallas DS1682 Elapsed Time Indicator (ETI) is provided to log the amount of
time the board is powered and the number of power cycles.
5.7.4 Temperature sensors
The SBC330 has two ADT7461 temperature sensors. One remotely monitors the
core temperature of the MPC8641D and the other monitors the ambient
temperature at its location on the PCB. The device is located directly underneath
the processor, next to the core PSU, which has been thermally modeled to be a hot
spot on the PCB.
The temperature sensors can generate interrupts to either processor core, via the
Local Bus FPGA, at two software‐defined thresholds.
Using the Secondary interrupt controller in the Local Bus Control FPGA, these
thresholds can optionally be configured to generate an interrupt and further can
be used to switch off the power supplies to the board. The current release of
firmware has this feature implemented but disabled. Future releases will allow
users to enable or disable the feature.
5.7.5 Power Supply manager
The SBC330 uses a Lattice ispPAC‐POWR1014A to monitor and sequence the on‐
2
board voltages. The device provides an I
C interface that can be used to access an
internal A‐to‐D converter to measure the value of each of the on‐board voltage
rails. Discrete inputs to and outputs from the device can also be monitored.
5.7.6 MPC8641D configuration EEPROM
On SBC330, the MPC8641 initial processor power‐up configuration is performed
by driving strapping signals using a Lattice LC4064B 48‐pin CPLD during the
time the board is in hard reset.
2
However, the I
C EEPROM is provided should further configuration information
need to be loaded into the device before software boots. The default VxWorks BSP
stores the VxWorks boot parameters and Ethernet MAC addresses in this device.
The processor's boot sequencer, which uses the EEPROM, is not enabled in
default firmware. If it is enabled, the device must be loaded with valid data
(including preamble and CRC) at all times for the processor to boot correctly. If
valid data is not read, then the Processor drives the HRESET_Request line active.
The EEPROM is write‐protected by default, and can be write‐enabled by clearing
the associated bit in the FPGA Miscellaneous Functions register at offset 0x28.
This bit may only be cleared when the VPX backplane signal, NVMRO negated.
Publication No. SBC330-0HH/3
Functional Description 39
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