Pci Interrupts; Power Management; Processor; Pci Express - GE SBC330 3U VPX Hardware Reference Manual

5.11 Power Management

44 SBC330 3U VPX Single Board Computer
Figure 5-5 SBC330 Interrupts

5.10.8 PCI Interrupts

PCI Express provides a mechanism for passing interrupts from legacy PCI
devices through the PCI Express fabric to the interrupt controller at the Root
Complex, using Assert_INTx and Deassert_INTx messages. These messages are,
however, subject to the same latency and non‐determinism as any other PCI
Express packet.
To reduce this latency, the SBC330 takes the interrupts from the USB controller
and mezzanines and routes them directly to the interrupt controller, via the Local
Bus Control FPGA, bypassing the fabric altogether.

5.11.1 Processor

All power management features of the processing cores, such as the
programmable power states (Doze, Nap and Sleep), Dynamic Power
Management, Instruction Cache Throttling and Dynamic Frequency switching,
are available to the software within the 8641D. No external hardware support is
required.

5.11.2 PCI Express

All PCI Express links support several power management features that are under
software control and require no hardware support. The SBC330 does not support
the WAKE* signal and recovery from a D3COLD state under auxiliary power.
Publication No. SBC330-0HH/3