Axis Timer Control Register; Test Register - GE SBC330 3U VPX Hardware Reference Manual

6.18 Test Register

Publication No. SBC330-0HH/3

6.17.4 Axis Timer control register

Chip Select CS2
Offset 0x0038
LAD Bit Reg Bit R/W
15 0 R/W
14 1 R/W
13 to 8 2 to 7 R/W
7 8 R/W
6 9 R/W
5 10 R/W
4 11 R/W
3 12 R/W
2 13 R/W
Not available in Rel 3 Firmware code
This 32‐bit read‐write register can be used by application software to complement
the two 16‐bit scratch registers.
Chip Select CS2
Offset 0x00A8
LAD Bit Reg Bit R/W
31 to 0 0 to 31 R/W
Description
AXIS Timestamp Master/Slave
0 = Slave (do not drive selected clock source
to backplane)
1 = Master (drive selected on-board clock
source to backplane)
Timestamp reset
0 = Not in reset – timer can free run.
1 = Reset the counters at the next clock
6 bit Prescaler. Uses the 100 MHz or 133 MHz
local bus clock (if Master)
Enable:
0 = Timer counters do not run
1 = Timer counters run
On-board clock source: 66. 6 MHz fixed
system clock
0 = Do not select 66.6 MHz on-board clock
1 = 66.6 MHz on-board clock selected
On-board clock source: Processor Local Clock
: 100, 133 MHz (DDR2 clock/2)
0 = Do not select Processor Local Bus clock
1 = Processor Local Bus clock selected
On-board clock source: 8 MHz fixed
0 = Do not select 8 MHz on-board clock
1 = 8 MHz on-board clock selected
On-board clock source: 250 KHz fixed
0 = Do not select 250 KHz on-board clock
1 = 250 KHz on-board clock selected
Description
Scratch register (useful for local bus debug) 0x00000000
Reset Value
0x0
0x0
0x000000
0x0
0x0
0x0
0x0
0x0
Reset Value
FPGA Registers 69