Flash Size Register; Watchdog Registers - GE SBC330 3U VPX Hardware Reference Manual

6.15 Flash Size Register

6.16 Watchdog Registers

Publication No. SBC330-0HH/3
There are no plans to offer variants that have different amounts of Flash memory.
However, as time progresses and Flash memory sizes increase, larger (in terms of
memory size) devices will be fitted. The SBC330 therefore provides this register so
that firmware knows how much Flash is fitted. The values in the register are a
simple GEIP/SBC330 mapping. The register is read‐only and initializes to its set
value.
Chip Select CS2
Offset 0x0050
LAD Bit Reg Bit R/W
15 0 R
14 1 R
13 2 R
The definitions are as follows. The Flash Size value relates to the total amount of
Flash on the board. The current build is for 256 MBytes of Flash (010
000 Illegal
b
001 128 MBytes
b
010 256 MBytes
b
100 512 MBytes
b
011 1024 MBytes
b
The Watchdog Timer monitors CPU activity and resets the system if the CPU does
not service a running (down‐counting) watchdog timer before it reaches zero.
This is useful for system recovery, for instance in the event that a core becomes
locked in an interrupt service routine from an errant interrupt source.
There are two identical 16‐bit (x 65536) Watchdog Timers, which can be controlled
from either a fast (10 MHz/100 ns period) or a slow (1.25 KHz/0.8 mS period)
clock. Using the fast clock, the watchdog timer range is 200 ns to 6.536 ms,
whereas using the slow clock, the Watchdog Timer range is 8 ms to 52.4 seconds
(the periods overlap so there are no gaps in the time out period that can be
chosen). The slow clock is used by default.
The period of the Watchdog Timer is programmed by setting a 16‐bit value in the
Watchdog Preset Register. The timer counts down from the value using the
selected clock, i.e. the Watchdog time‐out is calculated as follows:
(Preset Value * 0.8 ms) or (Preset Value * 0.1 μS)
The timer is enabled by writing '01' followed by '10' to the relevant bits of the
Watchdog Control register. Similarly, the watchdog is serviced by writing '01'
followed by '10' to the Stop & Clear bits of the register. The status of the Watchdog
can be read from this register at any point in time.
Description
Flash Size description bit 0
Flash Size description bit 1
Flash Size description bit 2
Reset Value
0x0
0x1
0x0
)..
b
FPGA Registers 65