Jtag - GE SBC330 3U VPX Hardware Reference Manual

5.12 JTAG

Publication No. SBC330-0HH/3
The SBC330 provides JTAG boundary scan facilities for all IEEE1149.1 and
IEEE1149.6‐compliant devices. The devices included in the JTAG chain depend on
the settings of the P12 JTAG jumper links. By means of QuickSwitch multiplexers,
the JTAG chain consists of:
• The Lattice isp1014A power manager.
• The Lattice MachX0 2280 FPGA and the Lattice LC4064 CPLD.
• Processor Only. For use with AC JTAG to test PCIe port 2 to VPX connectors.
• All the JTAG devices including the processor, but excluding the power
manager.
Table 5-14 JTAG Configuration
P12 Pins Linked JTAG Chain
Lattice PWR MAN isp1014A
5 & 6
FPGA and CPLD
(1 & 2) & (7 & 8)
(1 & 2) & (3 & 4) & (5 & 6) JTAG devices apart from processor AC electrical test (processor BGA
& (7 & 8)
1 & 2 All JTAG devices, inc processor
Any other combination Invalid arrangement
NOTE
(P12 Jumper (1-2) is dual function; it is also used in normal operation to distinguish between AMP
and SMP processing Modes. The default configuration has jumpers P12 (1-2) & (7-8) linked, which
defaults the processor to AMP mode operation and sets up the JTAG chain for reprogramming of
the FPGA or CPLD if required.
Usage
Programming PWR MANAGER on
virgin board
Programming PWR MANAGER on
virgin board
only)
Full JTAG electrical test
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Functional Description 45