P12 Header - GE SBC330 3U VPX Hardware Reference Manual

4.4 P12 Header

Publication No. SBC330-0HH/3
Table 4-2 Flash Jumper operation
Link Configuration
Pins 5 and 6 Not fitted
Pins 7 and 8 Not fitted
Binary (7-8)(5-6) 00
Address Memory Configuration
FFFF FFFF
Main
FFE0 0000
FFD0 FFFF
Alternative
FFC0 0000
FFB0 FFFF
Extended
FFA0 0000
FF90 FFFF
BANC
FF80 0000
The 256 KByte recovery boot image is stored in a hardware write‐protected Flash
sector. This is factory programmed and its contents cannot be overwritten by a
user.
This header is multi‐functional and allows for firmware reprogramming, factory
JTAG testing and AMP/SMP selection.
Users generally should not need to adjust the factory default link settings for
JTAG aspects of this header. They are set to allow firmware reprogramming of the
FPGA/CPLD, which is the most likely JTAG operation to be performed by a user.
However, it is important that a user sets the AMP/SMP jumper correctly for their
intended operation. AMP mode is the favored operational mode, which requires
P12 pins 1 and 2 to be linked.
Fitted Not fitted
Not fitted Fitted
01 10
Alternative Extended
Main BANC
BANC Main
Extended Alternative
Fitted
Fitted
11
BANC
Extended
Alternative
Main
Configuration 21