Backplane Status Register; Backplane Command Register; Hardware Exclusive Access Semaphore Register - GE SBC330 3U VPX Hardware Reference Manual

6.11 Hardware Exclusive Access Semaphore Register

60 SBC330 3U VPX Single Board Computer

6.10.1 Backplane status register

Chip Select CS2
Offset 0x003C
LAD Bit Reg Bit R/W
15 0 R
14 1 R
13 2 R

6.10.2 Backplane command register

Chip Select CS2
Offset 0x0040
LAD Bit Reg Bit R/W
15 0 R/W
14 1 R/W
The Semaphore register set is required so that both processor cores can make
exclusive access to shared resources such as Flash or I
Access Semaphore Register locks access to the 16‐bit Core Semaphore Register to
a single process. Before the Hardware Exclusive Access Semaphore Register is
ever read (i.e. on power‐up), it initializes to 0. At the first read, it returns 0 but
automatically sets after the local bus cycle that has read 0; a second or third read
to this register therefore returns a 1. If a process reads the Hardware Exclusive
Access Semaphore Register and a '0' is returned, it may then make reads and
writes to the Core Semaphore Register. Once the Core Semaphore Register has
been accessed, normally to take a semaphore for a resource, the Hardware
Exclusive Access Semaphore Register should be written to with a 0x0 to clear it. It
is the software's responsibility NOT to update the Core Semaphore Register, if the
Hardware Exclusive Access Semaphore Register returns a 1 when called.
The initial value is 0x0, but if this is read to obtain an initial value, the next read
returns 0x1.
Chip Select CS2
Offset 0x0070
LAD Bit Reg Bit R/W
15 0 R/W
Description Reset Value
NVMRO_STATE Depends on backplane signal
SYSRESET_STATE Depends on backplane signal
V46_SYSCON Depends on backplane signal
Description Reset Value
NVMRO drive Depends on backplane signal
SYSRESET drive Depends on backplane signal
Description
Read bit to take exclusive access
Write 0x0 to clear
2
C. The Hardware Exclusive
Reset Value
0x0
Publication No. SBC330-0HH/3