22 SBC330 3U VPX Single Board Computer
4.4.1 JTAG
Table 4-3 JTAG Jumpers on Header P12
P12 Pins
Function
1) Isolate ispPAC device from JTAG.
Pin 1 & pin 2
2) Select AMP/SMP mode.
Pin 3 & pin 4
Processor JTAG: chain or Emulator
Pin 5 & pin 6
Binary combination with pins 7 & 8
Pin 7 & pin 8
Binary combination with pins 5 & 6
Table 4-4 JTAG Multiplex Jumpers on P12 Header
Pins 5-6
Pins 7-8
Not fitted
Not fitted
Not fitted
Fitted
Fitted
Not fitted
Fitted
Fitted
• To program ispPWR‐PAC:
• To program Lattice FPGA
and CPLD:
• To test all JTAG chain:
• To test chain without
processor:
4.4.2 AMP/SMP Mode selection
To operate the SBC330 in Asymmetric Multiprocessing (AMP) mode, P12 pin 1
and pin 2 must be linked.
In AMP mode, the two cores may run either different operating systems or
different versions of the same operating system. To allow this, the MPC8641D
processor provides the ability to offset Core 1 accesses to the bottom of RAM by
256 MBytes (addresses 0x000 0000 to 0x1000 0000 are offset to 0x1000 0000 to
0x2000 0000). This allows both processing cores to maintain separate stacks and
private memory without any software intervention. This is the default mode
selected with this link not fitted. When the two processors are operating in
Symmetric Multiprocessing (SMP) mode, this feature is not desirable as both
processors need to share the same memory space.
Table 4-5 P12 AMP/SMP Mode
Pin 1 to Pin 2 Setting
Not linked
Linked
Binary
Function
00
TDO from chain – excluding processor
01
TDO from (FPGA-CPLD only) chain
10
TDO from ispPAC Power Manager
11
TDO from chain including Processor
Link P12 pin 5 to pin 6 only
Link P12 pins 1 to 2 and 7 to 8 only
Link P12 pins 1 to 2, 3 to 4, 5 to 6 and 7 to 8
Link P12 pin 1 to pin 2 only
Function
SMP Mode. No core 1 addressing offset
AMP Mode. Core 1 has 256 MByte memory offset
Action when fitted
PWR MAN isolated.
AMP mode selected.
Processor in chain
See next table
See next table
Publication No. SBC330-0HH/3