Core 0 And Core 1 Semaphore Registers - GE SBC330 3U VPX Hardware Reference Manual

Publication No. SBC330-0HH/3

6.11.1 Core 0 and Core 1 semaphore registers

The Core Semaphore registers are simple 16‐bit read/write registers that can only
be written to if the Hardware Exclusive Access Semaphore Register has its LSB set
to 1, indicating that a process has set it. Software determines the use of the bits –
they are not dedicated to any particular resource or function. This register
initializes to 0x0000.
Chip Select CS2
Offset 0x0074 (Core 0) and 0x0078 (Core 1)
LAD Bit Reg Bit R/W
15 0 R/W if HWA Sem taken
14 1 R/W if HWA Sem taken
13 2 R/W if HWA Sem taken
12 3 R/W if HWA Sem taken
11 4 R/W if HWA Sem taken
10 5 R/W if HWA Sem taken
9 6 R/W if HWA Sem taken
8 7 R/W if HWA Sem taken
7 8 R/W if HWA Sem taken
6 9 R/W if HWA Sem taken
5 10 R/W if HWA Sem taken
4 11 R/W if HWA Sem taken
3 12 R/W if HWA Sem taken
2 13 R/W if HWA Sem taken
1 14 R/W if HWA Sem taken
0 15 R/W if HWA Sem taken
Description Reset Value
Core 0/Core 1 0x0
Semaphore bit 0
Core 0/Core 1 0x0
Semaphore bit 1
Core 0/Core 1 0x0
Semaphore bit 2
Core 0/Core 1 0x0
Semaphore bit 3
Core 0/Core 1 0x0
Semaphore bit 4
Core 0/Core 1 0x0
Semaphore bit 5
Core 0/Core 1 0x0
Semaphore bit 6
Core 0/Core 1 0x0
Semaphore bit 7
Core 0/Core 1 0x0
Semaphore bit 8
Core 0/Core 1 0x0
Semaphore bit 9
Core 0/Core 1 0x0
Semaphore bit 10
Core 0/Core 1 0x0
Semaphore bit 11
Core 0/Core 1 0x0
Semaphore bit 12
Core 0/Core 1 0x0
Semaphore bit 13
Core 0/Core 1 0x0
Semaphore bit 14
Core 0/Core 1 0x0
Semaphore bit 15
FPGA Registers 61