Powerpc Processing Cores; Dual Processing Core Operation - GE SBC330 3U VPX Hardware Reference Manual

Publication No. SBC330-0HH/3

5.2.1 PowerPC processing cores

The MPC8641D contains two e600 high‐performance, 32‐bit, superscalar,
PowerPC processing cores, as used in the MPC7448 processor, clocked at up to
1.33 GHz. Each core includes:
• 32‐KByte Level 1 instruction and data caches
• 1‐MByte Level 2 backside cache with ECC
• 36‐bit physical addressing
• AltiVec Vector Unit
• Enhanced branch prediction capabilities
• MMU and integral FPU
• The e600 processing core implements a fully static architecture and offers
sophisticated power management capabilities.
The SBC330 is offered in three speeds. However, users can configure the speed of
the SBC330 in software and request firmware that supports intermediate speeds.
The SBC330 feeds a 66.6 MHz clock into the 8641D processor, and registers in the
FPGA allow a user to select the multipliers that are available within the 8641D to
achieve different speeds.
Current firmware supports up to MPX Bus (Platform)/Core speed options.
Contact your nearest GE Intelligent Platforms Sales Office or Agent for more
information.
Table 5-1 Processor Core Frequency Options
Core Frequency (MHz)
1000
1333
1500
User

5.2.2 Dual Processing Core operation

The MPC8641D contains two processing cores. Following reset, processing core 1
is prevented from accessing the MPX bus until it is enabled by core 0.
The two processing cores can run two different operating systems or two separate
instances of the same operating system. This is called Asymmetric Multi‐
Processing (AMP) mode. It is aided by the Low Memory Offset mode of the
MPC8641D, which applies a 256 MByte address offset to accesses by Core 1 to the
bottom of RAM (addresses 0x000 0000 to 0x1000 0000 are offset to 0x1000 0000 to
0x2000 0000). This allows both processing cores to maintain separate stacks and
private memory without any software intervention.
The two processor cores are also able to run a single operating system, with tasks
divided between them. This is called Symmetric Multi‐Processing (SMP) mode. In
this mode, the Low Memory Offset feature is not desirable as both processors
need to share the same memory space.
MPX Bus Frequency (MHz)
400
533
600
User
Functional Description 25