P0 Signal Definitions - GE SBC330 3U VPX Hardware Reference Manual

Table 9-3 P0/J0 Signal Definitions
Signal Direction
BP_CLK_N/P I/O
GA(0) -GA(4) Input
GAP~ Input
NC
NOT USED
P0_NVMRO I/O
P0_SYSRESET~ I/O
P3V3_AUX Input
SM(0) I/O
SM(1) I/O
TCK, TDI, Input
TMS,TRST~
TDO Output
VCC Input
Publication No. SBC330-0HH/3

9.2.3 P0 signal definitions

Description
VPX REF_CLK-
Geographical Addressing bits
Geographical Addressing Parity bit.
The sum of all GA bits, including the parity
bit, should be odd
Non Volatile Memory Read Only
VPX backplane System Reset
VPX 3.3V_AUX Power Input
System Management bus 0 CLK
System Management bus 0 DATA
JTAG test signals
JTAG TDO
VPX VS3 (5V) Power input
SBC330 Usage/Comment
SBC330 accepts as input to FPGA
GA0 to GA4 are pulled up to P3V3_AUX on
SBC330 via a 10k resistor. Value is read into
FPGA
GAP~ is pulled up to P3V3_AUX on SBC330
via a 10k resistor. Value is read into FPGA
Connector pin is not connected to any
signal
Backplane signal is not used by SBC330
Used by SBC330 as an input. Also can be
driven by SBC330 by FPGA if the SBC330 is
configured to be VPX slot 1 system
controller
SBC330 holds in reset till this signal is
negated. Can drive it for minimum 20mS if
VPX slot 1 controller
See Section A.2.1 for more details
Connects to the on-board BIT
Management Microcontroller (BMM). Allows
access to certain on-board resources from
2
an external I C master
Buffered - used for test / Programming
Fed from Quick Switch De-Multiplexer
See Section A.2.1 for more details
Connectors and Cables 79