Gpio Direction Register (0X642); Gpio Interrupt Enable Register (0X643); Table 3-17 Gpio Direction Register (0X642); Table 3-18 Gpio Interrupt Enable Register (0X643) - GE OpenVPX VPXcel6 SBC622 Hardware Reference Manual

3.2.33 GPIO Direction Register (0x642)

This defines which GPIO pins are used as outputs and which are inputs.

Table 3-17 GPIO Direction Register (0x642)

Bit Meaning
D7 GPIO7 direction
1 = Output
0 = Input (default)
D6 GPIO6 direction
1 = Output
0 = Input (default)
D5 GPIO5 direction
1 = Output
0 = Input (default)
D4 GPIO4 direction
1 = Output
0 = Input (default)
D3 GPIO3 direction
1 = Output
0 = Input (default)
D2 GPIO2 direction
1 = Output
0 = Input (default)
D1 GPIO1 direction
1 = Output
0 = Input (default)
D0 GPIO0 direction
1 = Output
0 = Input (default)

3.2.34 GPIO Interrupt Enable Register (0x643)

This defines which GPIO cells can generate interrupts.

Table 3-18 GPIO Interrupt Enable Register (0x643)

Bit Meaning
D7 GPIO7 interrupt enable
1 = Enabled
0 = Disabled (default)
D6 GPIO6 interrupt enable
1 = Enabled
0 = Disabled (default)
D5 GPIO5 interrupt enable
1 = Enabled
0 = Disabled (default)
D4 GPIO4 interrupt enable
1 = Enabled
0 = Disabled (default)
D3 GPIO3 interrupt enable
1 = Enabled
0 = Disabled (default)
D2 GPIO2 interrupt enable
1 = Enabled
0 = Disabled (default)
D1 GPIO1 interrupt enable
1 = Enabled
0 = Disabled (default)
D0 GPIO0 interrupt enable
1 = Enabled
0 = Disabled (default)
CPLD Control and Status Registers 61