Fpga; System Management Interrupt; Figure 4-1 Watchdog Timer Circuitry - GE C2K Hardware Reference Manual

MV64460
System
Controller
Interrupt
Controller
Watchdog
Timer
MPP Port

4.13 FPGA

The FPGA provides internal registers for the following functions (see "FPGA Registers" on
page 5-4):
• GPIO
• Counters/timers
• Interrupt Aggregation
• Reset management
• USARTs
• Device Bus management
• SMI#

4.13.1 System Management Interrupt

The FPGA can generate the System Management Interrupt (SMI) input to the processor. The SMI
is a level-sensitive processor input which the FPGA asserts if one or more of the following
interrupt sources are asserted:
• Backplane NMI# (maskable)
• Backplane DEG# (maskable)
• Backplane FAL# (maskable)
• Watchdog NMI# (maskable)
Each interrupt source is maskable through the FPGA SMI Mask Register (see "SMI Mask
Register" on page 5-14). These mask bits are set at reset.
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CPU_INT#
FPGA
SMI#
WD_NMI#
WD_EXP#
Watchdog timer circuitry
Figure 4-1
Functional Blocks
MPC7448
Processor
INT#
SMI#
SMI#
HRESET#
HRESET#
other board
devices
4-8