Break Address Register A (Bara) - Hitachi SH7750 series Hardware Manual

20.2.2

Break Address Register A (BARA)

Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
Note: *: Undefined
Break address register A (BARA) is a 32-bit readable/writable register that specifies the virtual
address used in the channel A break conditions. BARA is not initialized by a power-on reset or
manual reset.
Bits 31 to 0—Break Address A31 to A0 (BAA31–BAA0): These bits hold the virtual address
(bits 31–0) used in the channel A break conditions.
31 30
BAA31 BAA30
* *
R/W R/W
23 22
BAA23 BAA22
* *
R/W R/W
15 14
BAA15 BAA14
* *
R/W R/W
7 6
BAA7 BAA6
* *
R/W R/W
29 28
BAA29 BAA28
* *
R/W R/W
21 20
BAA21 BAA20
* *
R/W R/W
13 12
BAA13 BAA12
* *
R/W R/W
5 4
BAA5 BAA4
* *
R/W R/W
27 26
BAA27 BAA26
* *
R/W R/W
19 18
BAA19 BAA18
* *
R/W R/W
11 10
BAA11 BAA10
* *
R/W R/W
3 2
BAA3 BAA2
* *
R/W R/W
Rev. 4.0, 04/00, page 681 of 850
25 24
BAA25 BAA24
* *
R/W R/W
17 16
BAA17 BAA16
* *
R/W R/W
9 8
BAA9 BAA8
* *
R/W R/W
1 0
BAA1 BAA0
* *
R/W R/W