Hitachi SH7750 series Hardware Manual page 815

Table 23.17 Peripheral Module Signal Timing (cont)
Module Item
I/O Output data
ports delay time
Input data
setup time
Input data
hold time
'5(4Q
DMAC
setup time
'5(4Q hold
time
DRAKn
delay time
H-UDI Input clock
cycle
Input clock
pulse width
(high)
Input clock
pulse width
(low)
Input clock
rise time
Input clock fall
time
HD6417750
VF128
2
64 MHz*
Symbol Min Max
t — 10
PORTD
t 3.5 —
PORTS
t 1.5 —
PORTH
t 3.5 —
DRQS
t 1.5 —
DRQH
t — 10
DRAKD
t 50 —
TCKcyc
t 15 —
TCKH
t 15 —
TCKL
t — 10
TCKr
t — 10
TCKf
HD6417750
F167
HD6417750
F167I
HD6417750 HD6417750
SVF133 SF167
3
67 MHz* 83 MHz*
Min Max Min
— 10 —
3.5 — 3.5
1.5 — 1.5
3.5 — 3.5
1.5 — 1.5
— 10 —
50 — 50
15 — 15
15 — 15
— 10 —
— 10 —
HD6417750
BP200M
HD6417750
SBP200
4 5
100 MHz*
Max Min Max
8 — 6
— 3 —
— 1.5 —
— 3 —
— 1.5 —
8 — 6
— 50 —
— 15 —
— 15 —
10 — 10
10 — 10
Rev. 4.0, 04/00, page 807 of 850
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