10.2
Overview of CPG
10.2.1
Block Diagram of CPG
Figure 10.1 shows a block diagram of the CPG.
Oscillator circuit
Crystal
XTAL
oscillator
EXTAL
MD8
CKIO
CPG control unit
MD2
MD1
MD0
FRQCR: Frequency control register
STBCR:
Standby control register
STBCR2: Standby control register 2
PLL circuit 1
× 6
Frequency
divider 1
× 1/2
PLL circuit 2
× 1
Clock frequency
control circuit
FRQCR
Bus interface
Internal bus
Figure 10.1 Block Diagram of CPG
Frequency
divider 2
× 1
× 1/2
× 1/3
× 1/4
× 1/6
× 1/8
Standby control
circuit
STBCR
STBCR2
CPU clock (Iø)
cycle Icyc
Peripheral module
clock (Pø) cycle
Pcyc
Bus clock (Bø)
cycle Bcyc
Rev. 4.0, 04/00, page 199 of 850