Hitachi SH7750 series Hardware Manual page 442

Superh risc engine

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'5(4 Select (DS): Specifies either low level detection or falling edge detection as the

sampling method for the '5(4 pin used in external request mode.

In normal DMA mode, this bit is valid only in CHCR0 and CHCR1. In DDT mode, it is valid in

CHCR0–CHCR3.

Note: Level detection burst mode when TM = 1 and DS = 0

Edge detection burst mode when TM = 1 and DS = 1

Bit 18—Request Check Level (RL): Selects whether the DRAK signal (that notifies an external

device of the acceptance of '5(4) is an active-high or active-low output.

This bit is valid only in CHCR0 and CHCR1.

Bit 17—Acknowledge Mode (AM): In dual address mode, selects whether DACK is output in the

data read cycle or write cycle. In single address mode, DACK is always output regardless of the

setting of this bit.

In normal DMA mode, this bit is valid only in CHCR0 and CHCR1. In DDT mode, it is valid in

CHCR1–CHCR3.

Bit 16—Acknowledge Level (AL): Specifies the DACK (acknowledge) signal as active-high or

This bit is valid only in CHCR0 and CHCR1.

Low level detection

Falling edge detection

DRAK is an active-high output

DRAK is an active-low output

DACK is output in read cycle

DACK is output in write cycle

Active-high output

Active-low output

(Initial value)

Rev. 4.0, 04/00, page 431 of 850

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