Hitachi SH7750 series Hardware Manual page 816

Table 23.17 Peripheral Module Signal Timing (cont)
Module Item
$6(%5.
H-UDI
setup time
$6(%5.
hold time
TDI/TMS
setup time
TDI/TMS
hold time
TDO delay
time
ASE-PINBRK
pulse width
Notes: 1. Pcyc: P clock cycles
2. 64 MHz:
3. 67 MHz:
4. 83 MHz:
5. 100 MHz: V
Rev. 4.0, 04/00, page 808 of 850
HD6417750
VF128
2
64 MHz*
Symbol Min Max
t 10 —
ASEBRKS
t 10 —
ASEBRKH
t 15 —
TDIS
t 15 —
TDIH
t 0 10
TDO
t 2 —
PINBRK
V = 3.0 to 3.6 V, V
DDQ
V = 3.0 to 3.6 V, V
DDQ
V = 3.0 to 3.6 V, V
DDQ
(HD6417750F167, HD6417750SF167)
V = 3.0 to 3.6 V, V
DDQ
(HD6417750F167I)
= 3.0 to 3.6 V, V
DDQ
HD6417750
HD6417750
F167I
HD6417750 HD6417750
SVF133 SF167
3
67 MHz* 83 MHz*
Min Max Min
10 — 10
10 — 10
15 — 15
15 — 15
0 10 0
2 — 2
= typ. 1.5 V, Ta = –20 to +75°C, C
DD
= typ. 1.5 V, Ta = –20 to +75°C, C
DD
= typ. 1.8 V, Ta = –20 to +75°C, C
DD
= typ. 1.8 V, Ta = –40 to +85°C, C
DD
= typ. 1.8 V, Ta = –20 to +75°C, C
DD
F167
HD6417750
BP200M
HD6417750
SBP200
4
100 MHz*
Max Min Max
— 10 —
— 10 —
— 15 —
— 15 —
10 0 10
— 2 —
= 30 pF, PLL2 on
L
= 30 pF, PLL2 on
L
= 30 pF, PLL2 on
L
= 30 pF, PLL2 on
L
= 30 pF, PLL2 on
L
5
Unit Figure
t 23.68
cyc
t 23.68
cyc
ns 23.69
ns 23.69
ns 23.69
1
Pcyc* 23.70