Hitachi SH7750 series Hardware Manual page 469

For example, in the case shown in figure 14.15, DMAC transfer begins, at the earliest, five
CKIO cycles after the first sampling operation. DMAC transfer then continues until the end of
the number of data transfers set in DMATCR. '5(4 is not sampled during this time, and
therefore DRAK is output in the first cycle only.
In the case of dual address mode transfer initiated by an external request, the DACK signal can
be output in either the read cycle or the write cycle of the DMAC transfer according to the
specification of the AM bit in CHCR.
5. Burst Mode, Single Address Mode, Edge Detection
In burst mode using single address mode and edge detection, '5(4 sampling is performed
only in the first cycle.
For example, in the case shown in figure 14.21, DMAC transfer begins, at the earliest, five
cycles after the first sampling operation. DMAC transfer then continues until the end of the
number of data transfers set in DMATCR. '5(4 is not sampled during this time, and
therefore DRAK is output in the first cycle only.
In single address mode, the DACK signal is output every DMAC transfer cycle.
Suspension of DMA Transfer in Case of '5(4
With '5(4 level detection in burst mode or cycle steal mode, and in dual address mode or single
address mode, the external device for which DMA transfer is being executed can judge from the
rising edge of CKIO that DARK has been asserted, and suspend DMA transfer by negating
'5(4. In this case, the next DARK signal is not output.
Rev. 4.0, 04/00, page 458 of 850
'5(4 Level Detection
'5(4 '5(4