Hitachi SH7750 series Hardware Manual page 740

Table 22.2 Pin Functions (cont)
Pin
No. Pin Name
195 VDD
196 VSS
197 TMS
198 TCK
199 TDI
7567
200
201 VDD-PLL2
202 VSS-PLL2
203 VDD-PLL1
204 VSS-PLL1
205 VDD-CPG
206 VSS-CPG
207 XTAL
208 EXTAL
I: Input
O: Output
I/O: Input/output
Power: Power supply
Notes: 1. The VDDQ (3.3. V), VSSQ, VDD (1.8 V), and VSS pins must all be connected to the
system power supply, and power must be supplied continuously. Even if only the RTC
is operating (in standby mode), power must be supplied to all VDDQ, VSSQ, VDD, and
VSS pins, in the same way as for VDD-RTC and VSS-RTC.
2. Power must be supplied to VDD-PLL1/2 and VSS-PLL1/2 regardless of whether or not
the on-chip PLL circuits are used.
3. Power must be supplied to VDD-CPG and VSS-CPG regardless of whether or not the
on-chip crystal resonator is used.
4. Power must be supplied to VDD-RTC and VSS-RTC regardless of whether or not the
on-chip RTC is used.
5. VSSQ, VSS, VSS-RTC, VSS-PLL1/2, and VSS-CPG are not connected inside the
package.
6. The 5'5, RD/:55, CKIO2, and &.,25(1% pins are not provided on the QFP
package.
7. With the QFP package, the maximum external bus operating frequency is 83 MHz.
Rev. 4.0, 04/00, page 732 of 850
I/O Function
Power Internal VDD
(1.8 V)
Power Internal GND
(0 V)
I Mode (H-UDI)
I Clock (H-UDI)
I Data in (H-UDI)
I Reset (H-UDI)
Power PLL2 VDD (3.3V)
Power PLL2 GND (0V)
Power PLL1 VDD (3.3V)
Power PLL1 GND (0V)
Power CPG VDD (3.3V)
Power CPG GND (0V)
O Crystal resonator
I External input
clock/crystal
resonator
SRAM DRAM
Reset
Memory Interface
SDRAM PCMCIA MPX