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Bits 4 to 2—Area 2 and 3 Memory Type (DRAMTP2–DRAMTP0): These bits specify the type
of memory connected to areas 2 and 3. ROM, SRAM, flash ROM, etc., can be connected as
SRAM interface. DRAM and synchronous DRAM can also be connected.
Bit 4: DRAMTP2 Bit 3: DRAMTP1 Bit 2: DRAMTP0 Description
0
0
1
1
0
1
Note:
1. Selection of SRAM interface or MPX interface is determined by the setting of the
MEMMPX bit
2. When this mode is selected, 16 or 32 bits should be specified as the bus width for areas
2 and 3. In this mode the MD5 pin is designated for output as the 5$65 pin.
Bit 0—Area 5 and 6 Bus Type (A56PCM): Specifies whether areas 5 and 6 are accessed as
PCMCIA interface. The setting of these bits has priority over the MEMMPX and AnBST bit
settings.
Bit 0: A56PCM
0
1
Note: * The MD3 pin is designated for output as the &(5$ pin.
The MD4 pin is designated for output as the &(5% pin.
0
1
0
1
0
1
0
1
Description
Areas 5 and 6 are accessed as SRAM interface
Areas 5 and 6 are accessed as PCMCIA interface*
Areas 2 and 3 are SRAM interface or
1
MPX interface*
Reserved (Cannot be set)
Area 2 is SRAM interface or MPX
1
interface*
, area 3 is synchronous DRAM
interface
Areas 2 and 3 are synchronous DRAM
interface
Area 2 is SRAM interface or MPX
1
interface*
, area 3 is DRAM interface
Areas 2 and 3 are DRAM interface*
Reserved (Cannot be set)
Reserved (Cannot be set)
Rev. 4.0, 04/00, page 279 of 850
(Initial value)
2
(Initial value)
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