Hitachi SH7750 series Hardware Manual page 551

Superh risc engine
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Start of reception
Read ORER, PER, and FER flags
Read RDRF flag in SCSSR1
No
Read receive data in SCRDR1,
and clear RDRF flag
in SCSSR1 to 0
No
All data received?
Clear RE bit in SCSCR1 to 0
End of reception
Rev. 4.0, 04/00, page 540 of 850
in SCSSR1
PER or FER
or ORER = 1?
No
RDRF = 1?
Yes
Yes
Figure 15.10 Sample Serial Reception Flowchart (1)
1. Receive error handling and
Yes
Error handling
2. SCI status check and receive
3. Serial reception continuation
break detection: If a receive
error occurs, read the ORER,
PER, and FER flags in
SCSSR1 to identify the error.
After performing the
appropriate error handling,
ensure that the ORER, PER,
and FER flags are all cleared to
0. Reception cannot be
resumed if any of these flags
are set to 1. In the case of a
framing error, a break can be
detected by reading the value
of the RxD pin.
data read : Read SCSSR1 and
check that RDRF = 1, then read
the receive data in SCRDR1
and clear the RDRF flag to 0.
procedure: To continue serial
reception, complete zero-
clearing of the RDRF flag
before the stop bit for the
current frame is received. (The
RDRF flag is cleared
automatically when the direct
memory access controller
(DMAC) is activated by an RXI
interrupt and the SCRDR1
value is read.)

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