Hitachi SH7750 series Hardware Manual page 812

Superh risc engine
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Figure 23.59 Memory Byte Control SRAM Bus Cycles
(1) Basic Read Cycle (No Wait)
(2) Basic Read Cycle (One Internal Wait)
(3) Basic Read Cycle (One Internal Wait + One External Wait)
Rev. 4.0, 04/00, page 804 of 850

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