Bit:
Bit name:
Initial value:
R/W:
Bit:
Bit name:
Initial value:
R/W:
Bit:
Bit name:
Initial value:
R/W:
Bit:
Bit name:
Initial value:
R/W:
Bits 31, 27, 23, 19, 15, 11, 7, and 3—Reserved: These bits are always read as 0, and should only
be written with 0.
Bits 30 to 28— DMAIW-DACK Device Inter-Cycle Idle Specification (DMAIW2–
DMAIW0): These bits specify the number of idle cycles between bus cycles to be inserted when
switching from a DACK device to another space, or from a read access to a write access on the
same device. The DMAIW bits are valid only for DMA single address transfer; with DMA dual
address transfer, inter-area idle cycles are inserted.
Bits 4n + 2 to 4n—Area n (6 to 0) Inter-Cycle Idle Specification (AnlW2–AnlW0): These bits
specify the number of idle cycles between bus cycles to be inserted when switching from external
memory space area n (n = 6 to 0) to another space, or from a read access to a write access in the
same space.
Rev. 4.0, 04/00, page 282 of 850
31
30
—
DMAIW2 DMAIW1 DMAIW0
0
1
R
R/W
R/W
23
22
—
A5IW2
A5IW1
0
1
R
R/W
R/W
15
14
—
A3IW2
A3IW1
0
1
R
R/W
R/W
7
6
—
A1IW2
A1IW1
0
1
R
R/W
R/W
29
28
1
1
R/W
21
20
A5IW0
1
1
R/W
13
12
A3IW0
1
1
R/W
5
4
A1IW0
1
1
R/W
27
26
—
A6IW2
A6IW1
0
1
R
R/W
R/W
19
18
—
A4IW2
A4IW1
0
1
R
R/W
R/W
11
10
—
A2IW2
A2IW1
0
1
R
R/W
R/W
3
2
—
A0IW2
A0IW1
0
1
R
R/W
R/W
25
24
A6IW0
1
1
R/W
17
16
A4IW0
1
1
R/W
9
8
A2IW0
1
1
R/W
1
0
A0IW0
1
1
R/W