Table of Contents
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13.1.1 Features................................................................................................................ 257
13.1.2 Block Diagram..................................................................................................... 259
13.1.3 Pin Configuration................................................................................................. 260
13.1.4 Register Configuration......................................................................................... 264
13.1.5 Overview of Areas ............................................................................................... 265
13.1.6 PCMCIA Support ................................................................................................ 268
13.2 Register Descriptions ........................................................................................................ 272
13.2.1 Bus Control Register 1 (BCR1) ........................................................................... 272
13.2.2 Bus Control Register 2 (BCR2) ........................................................................... 280
13.2.3 Wait Control Register 1 (WCR1)......................................................................... 281
13.2.4 Wait Control Register 2 (WCR2)......................................................................... 283
13.2.5 Wait Control Register 3 (WCR3)......................................................................... 291
13.2.6 Memory Control Register (MCR)........................................................................ 292
13.2.7 PCMCIA Control Register (PCR)........................................................................ 299
13.2.8 Synchronous DRAM Mode Register (SDMR) .................................................... 302
13.2.9 Refresh Timer Control/Status Register (RTSCR) ................................................ 304
13.2.10 Refresh Timer Counter (RTCNT)........................................................................ 306
13.2.11 Refresh Time Constant Register (RTCOR) ......................................................... 306
13.2.12 Refresh Count Register (RFCR) .......................................................................... 307
13.2.13 Notes on Accessing Refresh Control Registers.................................................... 308
13.3 Operation .......................................................................................................................... 309
13.3.1 Endian/Access Size and Data Alignment............................................................. 309
13.3.2 Areas .................................................................................................................... 320
13.3.3 Basic Interface ..................................................................................................... 324
13.3.4 DRAM Interface .................................................................................................. 332
13.3.5 Synchronous DRAM Interface ............................................................................ 350
13.3.6 Burst ROM Interface............................................................................................ 374
13.3.7 PCMCIA Interface............................................................................................... 377
13.3.8 MPX Interface...................................................................................................... 388
13.3.9 Byte Control SRAM ............................................................................................ 405
13.3.10 Waits between Access Cycles.............................................................................. 410
13.3.11 Bus Arbitration .................................................................................................... 411
13.3.12 Master Mode ........................................................................................................ 415
13.3.13 Slave Mode .......................................................................................................... 416
13.3.14 Partial-Sharing Master Mode............................................................................... 416
13.3.15 Cooperation between Master and Slave............................................................... 418
13.3.16 Notes on Usage .................................................................................................... 418
14.1 Overview........................................................................................................................... 419
14.1.1 Features................................................................................................................ 419
14.1.2 Block Diagram..................................................................................................... 421
14.1.3 Pin Configuration................................................................................................. 422
.......................................... 419
Rev. 4.0, 04/00, page xv of 20
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